it has been decades since i designed a UART; however, if I recall it well, there is a 16x clock at the receiver. Thus, when you say “I am now planning for asynchronous clocks testing where the Tx and Rx clocks would be [b]slightly different in frequency and phase” I don’t really understand it. Typically, the tx 16x clock and rx 16x clock are of the same frequency, but not the same phase. Those frequencies can vary a bit and the 16x rate allows for some s=deviations between the rx and tx clock. Is this what you mean?
How am I going to assert() when I have two different clocks ?
You could simply have 2 counters, one for the tx and one for rx.
Let those clocks count for 100 or 1000 cycles, and then compare the values of the counts. From there you can assess the frequency differences. SVA would not do too well on this.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
See Paper: 1) VF Horizons:PAPER: SVA Alternative for Complex Assertions - SystemVerilog - Verification Academy
2) http://systemverilog.us/vf/SolvingComplexUsersAssertions.pdf