Structs and Unions

SystemVerilog
,
1 
struct {
  string name;
  int roll_no;
  int age;
}student;
typedef union packed{
  bit [31:0]age1;
  int rollno;
 }student1;
module top;
  student1 s1;
  initial begin
    student = '{name:"ABC",roll_no:41,age:21};
    s1.age1 = 32'h40;
    $display("%p",s1);
   #10; s1.rollno=32;
      $display("%p",s1);
  $display("%p",student);
   end
endmodule

when i execute this code i am getting the output as:
'{age1:'h40}
'{age1:'h20}
'{name:“ABC”, roll_no:41, age:21}
I think i should get age1 in first display and rollno in the second, can anyone tell me whats wrong?

2

In reply to Manoj J:

A packed union does not store any information about the last member that was written. You may want to look at tagged unions if that is important to you.

3

In reply to dave_59:

I am a novice in System Verilog, I was just trying to understand how structs and unions work

A packed union does not store any information about the last member that was written. Yo

Sorry dave, I didn’t understand it, can you explain with an example
Thank you
Manoj

4

In reply to Manoj J:

Read the deffiniton of the %p format specifier.

5

In reply to dave_59:

Read the deffiniton of the %p format specifier

Thanks dave, I went through the section 21.2.1.7 Assignment Pattern format of LRM-2012,It says that it only displays the first declared element of packed unions.