Struct in System verilog

SystemVerilog
,
4

In reply to dave_59:

I got the error as

ERROR VCP5211 “Aggregate literal is not allowed in this context.” “testbench.sv” 11 80

Here is the code

module tb;
typedef struct{
int age;
string name;
byte classes;
bit status;
}student_data;

student_data base;
initial begin
base ={‘{10,“John”,2,1},’{11,“Paul”,2,0},'{12,“George”,2,0}, '{13,“Ringo”,2,0}};
$display(“student details=%p”,base);
end
endmodule