String variable usage

SystemVerilog
1

Hi,
In System verilog, is there a way to use the string variable in a statement?
Example:

Here the input string is a register name, and using the register name I’m trying to call the get_reset() task to get the reset value of the register. The below code is not working, because the sting variable “xyz” is not allowed as such. Is there any alternate way to achieve this?

task abc(input string xyz);
aaa.bbb.xyz.get_reset();
endtask

2

If bbb is a uvm_reg_block , you could do

task abc(input string xyz);
  uvm_reg r;
  if ((r = aaa.bbb.get_reg_by_name(xyz)) != null)
    ... = r.get_reset();
  else
    `uvm_error("RNF",$sformatf("Register \"%s\" not found",xyz))
endtask

However, looking up things by a string name is very costly for performance. If you know the string name of a register, why don’t you pass the actual name of the register to the task.

3

In reply to dave_59:

Hi Dave,
Since I’m not able to use the string variable directly, I too implemented the same logic to get the reset value in my environment. But after that when I try to get the register value using the backdoor access read function, I’m facing the problem.

ral_model.reg_name.read(status,reset_act,vmm_ral::BACKDOOR,domain);

Here I need to pass the register name in the place of “reg_name”.

4

In reply to Dhana:

You cannot use strings in place of variable names. Ultimately, you are trying to get a handle to class object and call its read() method. If the vmm RAL model has a way of looking up registers by name, you will have to use that method first. If it does not, you will have to create associative array of register objects indexed by their string name.