String concatenation

SystemVerilog
,
1

Hi,
I have a code as shown below.

 logic[31:0] mem1[0:1024];
 logic[31:0] mem2[0:1024];
 logic[31:0] mem3[0:1024];
 filename = {/a/b,"/c/d/a1.hex"};
 $readmemh(filename,mem1);
 filename = {/a/b,"/c/d/a2.hex"};
 $readmemh(filename,mem2); 
 filename = {/a/b,"/c/d/a3.hex"};
 $readmemh(filename,mem3);

and so on till a100.hex,mem100

i wanted to use loop as shown below.

for(int i =1;i<100;i++)
begin
 filename = {/a/b,"/c/d/ai.hex"};
 $readmemh(filename,memi);
end

where “i” should be replaced with loop count number using string concatenation.Can someone help with the right way to achieve it.

Regards,
Sravan

2

In reply to sra1dreddy:

The right way is to use an array. You cannot dynamically form identifiers from other variables.

logic[31:0] mem[1:100][0:1024];
foreach(mem[I]) begin
    filename = $sformatf("/a/b/c/d/a%0d.hex",i);
    $readmemh(filename,mem[i]);
end
3

In reply to dave_59:
Hi Dave,
Iam getting below error
Illegal argument to memory task

Argument no. 2 to $readmemh must be a memory
Argument given is
this.mem[i].
Please correct the system task call and recompile

may i know how to specify mem index?

Regards,
Sravan