Streaming operators to convert concatenate 8 bit array into a 32 bit array

SystemVerilog
, ,
1

Hi I am trying to concatenate 8bit array into a 32 bit array. Below is the code

bit [7:0] data8[];
bit [31:0] data32[];

data8 = new[3];
data8[0]=8'hE0;
data8[1]=8'h3F;
data8[2]=8'h62;

data32 = {<<32{{<<8{temp_data8}}}};

I am expecting data32 to be 32’h623FE0 but the output I get is 32’h623FE000. Can you please let me know what am I doing wrong here?

TIA.

2

You problem is you are trying to stream 24 bits of data into a 32 bit variable. The streaming operator left justifies.

Here are a couple of ways to add 8 more bits

module top;
  bit [7:0] data8[];
  bit [31:0] data32[];
initial begin
  data8 = new[3];
  data8[0]=8'hE0;
  data8[1]=8'h3F;
  data8[2]=8'h62;
  data32 = {<<8{data8,8'h00}}; // could also use another variable
  $displayh(data32);
  data8 = new[4];
  data8[0]=8'hE0;
  data8[1]=8'h3F;
  data8[2]=8'h62;
  data8[3]=8'h00;
  data32 = {<<8{data8}};
  $displayh(data32);
end
endmodule