Streaming Operators (<<,>>) - how do they exactly work?

SystemVerilog
, ,
1

Hi All,

  1. Streaming Operators (<<,>>) - how do they exactly work @SystemVerilog? Do they perform shifts?

  2. $display(“@%0dns a %x b %x c %x”,$time,a,b,c);
    what does the %x mean here? What’s format is for?

Thank you!

2

Do have a copy of the LRM? If not, see Get your free copy of the IEEE 1800-2023 SystemVerilog LRM - Verification Horizons for $display formats

Also see What is meaning of Streaming Operator - SystemVerilog - Verification Academy

3

Thanks! Somehow I missed this post!