Streaming Operators (<<,>>) - how do they exactly work?

SystemVerilog
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Hi All,

  1. Streaming Operators (<<,>>) - how do they exactly work @SystemVerilog? Do they perform shifts?

  2. $display(“@%0dns a %x b %x c %x”,$time,a,b,c);
    what does the %x mean here? What’s format is for?

Thank you!

2

Do have a copy of the LRM? If not, see http://go.mentor.com/get-1800 for $display formats

Also see what is meaning of Streaming Operator | Verification Academy

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Thanks! Somehow I missed this post!