Streaming 32-bit to 8-bit

SystemVerilog
,
5

In reply to dave_59:

In reply to Robert.Lanier:
If you really wanted to use the streaming operator, data would have to be defined as a queue.

module top;
bit [31:0] queue[$] = {32'h01234567,32'h89ABCDEF};
bit[7:0]   data[$];
initial begin
queue.reverse;
data = {<<8{queue}  };
$displayh("%p",data);
end
endmodule

Is this because the LHS and RHS need to be of the same type when using a streaming operator?