In reply to dave_59:
In reply to Robert.Lanier:
We don’t know the byte ordering you want. It would help if you gave some sample values and showed how you wanted data to be streamed. For example
module top;
bit [31:0] queue[$] = {32'h01234567,32'h89ABCDEF};
bit[7:0] data;
initial
foreach(queue[i])
for (int j=0; j<4; j++) begin
data = queue[i][j*8+:8];
$displayh(data);
end
endmodule
Displays
# 67
# 45
# 23
# 01
# ef
# cd
# ab
# 89
I should have mentioned I am trying to fetch LSB first, thank you for pointing this out.
I had started using the same solution you have shown, but preferred to use the streaming concept rather rather than specific values from the data word. However, after reviewing section 11.5.1 Vector bit-select and part-select addressing of the SystemVerilog LRM (1800-2017), this is the solution I was looking for.
Thank you again for the help!