Storing data based on address

SystemVerilog
,
1 

module st_data;
// wanted to store data based on the addresses 
typedef struct {bit [5:0] dst_addr; bit [57:0] o_data;}  outdata; 
typedef struct {bit [5:0] src_addr; bit [57:0] i_data;}  indata; 
  
 outdata out_data_q [26][$]; 
 indata out_data_q [26][$];

// dst_addr 0 to 26
// src_addr 0 to 26
// have to store accordingly

//******* for out_data ********//
always @(posedge clk iff reset) begin
  //if control is true (valid && ready)
  // out_data_q.push_front
  // based on dst_addr push in that queue;
  // and based on the dst_addr pop from that queue;
end

endmodule: st_data

TIA

2

In reply to m_r_m:

You need to explain better what you are trying to accomplish.

You could certainly do

out_data_q[outdata.dst_addr]].push_front(outdata);

But that seems like you would be wasting a lot of space because the dst_addr of each queue element you be the same for each index of the queue.

It might help to explain with a few scenarios of data that need to be operated on.

3

In reply to dave_59:
Thanks Dave.


bit [63:0] o_data_pkt [26:0]; // [58:63] is dst_addr and [58:0] is data
bit [63:0] i_data_pkt [26:0]; // [58:63] is src_addr and [58:0] is data

//I am trying to store the data based on the addr, so I can access the data based on address (from out_data side) and compare with the in_data (based on address)
// can we do this w/ associative array instead ?

typedef struct {bit [5:0] dst_addr; bit [57:0] o_data;}  outdata;
bit [56:0] o_data_pkt [int][26:0];
/*
if(o_data_pkt.exists (dst_addr)) begin
   o_data_pkt = outdata[dst_addr]; 
end //??
*/