Static variables/local variables in tasks

SystemVerilog
, ,
1 
module test();

task dummy_task(input int x,string str);
fork
	begin
		#x;
	end
	
	begin
		#10;
	end
join_any

disable fork;
$display("%s is disabled at t = %t",str,$time);
endtask

initial
	fork
		begin
			#2;
			dummy_task(5,"call_1");
		end
		begin
			#1;
			dummy_task(15,"call_2");
		end
	join
	
endmodule

The display results into the following:
“call_1 is displayed at 7”
“call_1 is displayed at 11”
My question is from the above code, since the variables are static in the task(not declared automatic), the “x” variable gets overwritten at #2 with value = 5, so shouldn’t the result be something like this:
“call_1 is displayed at 6”
“call_1 is displayed at 7” ?? I mean shouldn’t that “#15” be replaced by “#5”? If it’s not getting replaced then why is it not getting replaced?

2

In reply to Ritvik Kumar:

The results you see are correct. A delay control expression gets evaluated at the point when the delay control suspends the process. There is no re-valuation of the expression if any of it operands change.

3

In reply to dave_59:

Thank you Dave for your answer.
But do you think you can shed some more light on this statement “A delay control expression gets evaluated at the point when the delay control suspends the process” I did not understand this!

4

In reply to Ritvik Kumar:

module top;
  int D;
  
  initial begin : process1
    #2 $display("Start waiting for #delay(%0d) at time ",D*2,$time);
    
    #(D*2);
    
    $display("Done waiting for #delay(%0d) at time ",D*2,$time);
   
  end
  
  initial begin : process2
    D = 5;
    #4 D = 20;
  end
endmodule

The delay control expression #(D*2) suspends process1 at time 2 to resume at time 12. Changing D at anytime while process1 is suspended will not change the time it resumes. The same applies to #(x) in your example.