Static Variable with different parameterized class value

SystemVerilog
1

Piece of SV Code :

class abc #(int a=10);
static int b =a;
endclass

module mod();
abc a1;
abc#(50) a2;

initial
begin
$display(“b=%0d, b=%0d, b=%0d”,a1.b,a2.b,a1.b);
end
endmodule:mod

Output :
b=10, b=50, b=10.

Does it mean, a1.b and a2.b are allocated on different memory space or same.?

2

In reply to Pratik PK:

Hmm… I also observed the same thing.

When the class is not a parameterized class then everything is working as expected. So something is there with parameterized classes.

class abc;
static int b;
endclass

module mod(); 
abc a1;
abc a2;

initial
begin
 a1.b =10;
 a2.b =20;
$display("b=%0d, b=%0d, b=%0d",a1.b,a2.b,a1.b);
end
endmodule:mod

This code will output : b=20, b=50, b=20

3

LRM says following:

It is often useful to define a generic class whose objects can be instantiated to have different array sizes or data types. This avoids writing similar code for each size or type and allows a single specification to be used for objects that are fundamentally different and (like a templated class in C++) not interchangeable.

It says that it is a generic class. So when i use same parameter value “static” variables are same across those two.

class abc #(int a=10);
static int b =a;
endclass

module mod(); 
abc #(50) a1;
abc #(50) a2;

initial
begin
a1.b =25;
$display("b=%0d, b=%0d, b=%0d",a1.b,a2.b,a1.b);
end
endmodule:mod

result of above code: b=25, b=25, b=25