Static property access and instance declaration of a class

SystemVerilog
,
1

Hi,
Can someone please help me understand the problem with the below code ? As per my understanding static member is independent of the class instance, so this should work.

class packet;
  bit [31:0] addr;
  static bit [31:0] id;

  function void display(bit [31:0] a, bit [31:0] b);
    $display("Values are %0d %0d", a, b);
  endfunction
endclass

module sro_class;
  initial begin
    // Access and modify static member without instance
    packet::id = 20;

    // Create an instance of the class
    packet p;
    p = new();

    // Use instance to call non-static method
    p.display(packet::id, 2);

    // Access static member via instance (not recommended but works)
    $display("Static id via instance: %0d", p.id);
  end
endmodule
2

The problem with your code is unrelated to static class members. You cannot have a variable declaration (packet p)in the middle of a procedural block of code. It must come before any procedural statements, or put the declaration p outside the procedural begin/end block.