Static method

SystemVerilog
, ,
1 

class Class1;
 static  int value;
 
 function inc();

	value++;
  
   $display("value=%d",value);
endfunction

endclass

module example;
Class1 c1;
Class1 c2;
initial
begin	
 c1.value=2;
  c1.inc;
  c1.inc;
  c2.inc;
  c1.inc;
end

endmodule

output:
value=3
value=4
value=5
value=6
Here the function inc is not a static method, but still i’m able to access the inc function without creating an object. Why is this so.
Normally we can access functions by creating the object but here i’m able to get the output values.

  1. Is this because the variable is static ?
  2. my method is not a static. How can i get the ‘value’ variable
    what is the exact difference between static tasks/functions and automatic tasks/functions ? please explain with a clear example | Verification Academy
    I saw this entire discussion. I understood the static and automatic methods. Dave said we cannot use static keyword. it will lead to mistakes.
2

In reply to abhishek403:

See Why is my code not failing when accessing non static method from not static class? | Verification Academy

3

In reply to dave_59:

→ it would not be until the method tries to reference the null this handle that you would see an error.
I have not understood this point dave.

4

In reply to abhishek403:

Change your class example to

class Class1;
 static  int value;
         bit flag;
 function void inc();
 
	if (value++> 3) flag = 1;
        
   $display("value=%d",value);
endfunction
 
endclass

and see when it fails.