Static and automatic class object difference

SystemVerilog
1

Hi,

for a simple code
-------code-----------
class A; endclass

module top;
initial begin
A a = new();
end
endmodule

on compilation may give u a message
like “a is implicitly static you must explicitly declare it as static or automatic or separate out deceleration and initialization of ‘a’”

from the message what it says 3 solutions can be

  1. “static A a = new();”
  2. “automatic A a = new();”
  3. “A a;
    a = new();”

I am curious what differences with ‘a’ being static or automatic?

Thanks

2

In reply to Parveez ahamed:

Compiled the same code in VCS. But i didnt get any compilation message like above… Code runs smoothly.

3

In reply to srvm:

Hi

I ran the code on Edaplayground.com and could see the warnings!\

-BR
Hash

[2014-05-15 08:12:45 UTC] vlib work && vlog -writetoplevels modelsim.tops ‘-timescale’ ‘1ns/1ns’ ‘-mfcu’ ‘+acc=rmb’ ‘-sv’ ‘-suppress’ ‘2181’ design.sv testbench.sv && vsim -c -do “onElabError resume; run -all; exit” -f modelsim.tops ‘-suppress’ ‘3829’
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
**** Warning: design.sv(6): (vlog-LRM-2244) Variable ‘a’ is implicitly static. You must explicitly declare it as static or automatic.**
– Compiling package design_sv_unit
– Compiling module top
**** Warning: design.sv(6): (vlog-LRM-2244) Variable ‘a’ is implicitly static. You must explicitly declare it as static or automatic.**

Top level modules:
top
Reading /altera-quartus/13.1/modelsim_ase/tcl/vsim/pref.tcl

10.1d

vsim -do {onElabError resume; run -all; exit} -c -suppress 3829 top

Loading sv_std.std

Loading work.design_sv_unit

Loading work.top

onElabError resume

resume

run -all

exit

Done

4

In reply to Subhash:

This is tool support issue. The tool may not follow LRM strictly.

5

See Section 6.21 Scope and lifetime of the 1800-2012 LRM. Your confusion (as well as many other people’s) with this is main reason the LRM requires an error message.

Static vs. automatic is manly a difference in lifetime, but also initialization. Static variables initialize before time 0, and automatic variable initialize when the block is procedurally activated.

In most programming languages, variables declared inside of procedural blocks are automatic by default, but in Verilog, the default is static. SystemVerilog was able to change the default for class methods to match C/C++, but could not do it for backward compatibility with legacy Verilog blocks.

Variable initialization was a relatively new feature in Verilog, but so many people missed the fact that when they declared a variable inside a procedural looping construct, the variable only got initialized once at time 0, not each iteration of the loop.

module top;
initial repeat (10) begin
    A a = new();
    end
endmodule

By old Verilog rules, a is initialized only once.

6

In reply to dave_59:

LRM keep using this kind of examples. But I also see some tools compile this code too.

Thanks