In reply to Shipra_s:
I think what’s confusing the matter is I incorrectly typed my run_phase initially.
There are three tasks: update_regs(), which calls a function write_regs(), which starts a sequence, write_seq. set_video_seq, once spawned can run for x amount of frames. At the end of every frame, update_reqs() occurs, which then starts another write_seq.
task base_test_c::run_phase(uvm_phase phase);
`uvm_info(get_type_name(),"RUNNING",UVM_LOW)
phase.raise_objection(this);
`uvm_info(name, "raise objection in base test", UVM_MEDIUM)
fork
set_video_seq(phase);
update_regs();
begin
wait (!top.u_dut.rst);
OTHER CODE IS HERE......
end
join
`uvm_info(name, "drop objection in base test", UVM_MEDIUM)
phase.drop_objection(this);
endtask : run_phase
task base_test_c::set_video_seq(uvm_phase phase);
phase.raise_objection(this);
`uvm_info(name, "raise objection", UVM_MEDIUM)
seq_h = video_seq_c::type_id::create("video_seq", this);
seq_h.start(tb_env_h.env_h.video_in_env_h.agent_h.sequencer_h);
`uvm_info(name, "drop objection", UVM_MEDIUM)
phase.drop_objection(this);
endtask : set_video_seq
task base_test_c::write_regs();
write_seq_c write_seq_h;
int mem_array [];
mem_array = new[axi_reg_pkg::REG_SIZE_W32];
foreach (reg.w32[i]) mem_array[i] = reg.w32[i];
`uvm_info(name,$sformatf("\n%p",reg.id),UVM_NONE);
write_seq_h = write_seq_c::type_id::create("write_reg_seq");
write_seq_h.set_start_addr(0);
write_seq_h.set_array_by_ref(mem_array);
write_seq_h.start(tb_env_h.ram_env_h.agent_h[0].sequencer_h);
endtask : write_regs
What was not included before is update_regs(). Here is a simplified version of it.
//------------------------------------------------------------------------
//Update registers every frame
//------------------------------------------------------------------------
task base_test_c::update_regs();
cur_frame = proc_cfg_h.start_on_frame;
repeat (proc_cfg_h.num_frames) begin : P_update_regs
reg_bank.id.r.s.reg1 = '{ bypass : 1'b0
, value : 5'd30
, default : '0
};
reg_bank.id.r.s.reg2 = '{ bypass : 1'b0
, value : 5'd40
, default : '0
};
`uvm_info(name,$sformatf("Updating Registers"),UVM_MEDIUM);
write_regs();
@(proc_cfg_h.in_video_bus_cfg_h.driver_end_of_frame) cur_frame++;
//wait until start of next frame before changing registers
//assuming all processing is done during 1 frame time
@(proc_cfg_h.in_video_bus_cfg_h.driver_start_of_frame);
end : P_update_regs
endtask : update_regs
I would attach waveforms but can’t figure out how