how to check variables(more than one) are stable or not using $stable in SV Assertions?
please help…
In reply to aditya93:
how to check variables(more than one) are stable or not using $stable in SV Assertions?
please help…
Per 1800, $stable returns true if the sampled value of the expression did not change between the sampled value at the previous cycle and the sampled value at the current cycle. Otherwise, it returns false. $changed is a complement to $stable; $changed returns true if the sampled value of the expression changed. Otherwise, it returns false.
Below is an application example from my SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
/* Application example: Once req_valid is asserted, req_length should not change its value until req_ready is sampled to a value of 1'b1.
Two possible solutions: // /ch4/4.2/reqstable.sv */
ap_version1: assert property(@(posedge clk)
$rose(req_valid) |=> $stable(req_length) until $rose(req_ready));
ap_version2: assert property(@(posedge clk) $rose(req_valid) |=> $stable(req_length)[*0:$] ##1 $rose(req_ready) );
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115