SPI frame format

SystemVerilog
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1

Hi,
How the spi frame format is there for the back to back transfers. is it like ahb which has address phase and data phase in spi also?, otherwise spi is not fullduplex we transfer the address then data from mosi line for the write transaction ideally in write transfer miso line will not be active for whole 16 cycles how it is called fullduplex when the slave is not driving the data can someone explain?.

here i am saying that the both the mosi and miso line data must be valid to spi be fullduplex.

Thanks.

2

In reply to m_v:

SPI (Serial Peripheral Interface) is actually considered a complete duplex communication protocol, but it works differently than bus-based protocols like AHB (Advanced High-performance Bus) In SPI, there is no separation of address and data phases between strictly as you can check it in the bus protocol.

Here is basic information about SPI usage:

Master-slave interaction:

SPI involves communication between the master and one or more slaves.
The master performs the clock (SCLK) to initiate communication.
Clock and data lines:

The SPI generally consists of four lines:
SCLK (Serial Clock): Developed by the owner, it synchronizes data transmission.
MOSI (Master Out, Slave In): The master sends data to the slave.
MISO (Master In, Slave Out): The slave sends data to the master.
SS/CS (Slave Select/Chip Select): Used to select the target slave.
Frame format:

Sends data in SPI frames.
Each frame is typically one byte of data, but can be many depending on the configuration.
The bit is usually the Most Significant Bit (MSB) and is transmitted first.
The SS/CS line is used to enable/activate the slave for communication.
Full duplex operation:

Full-duplex means that data can be sent and received at the same time.
This is achieved by having separate MOSI and MISO lines in the SPI.
During the writing operation, the master sends data to the MOSI line, and the slave can send back some information on the MISO line.
Running hours:

The clock continues to run even when there is no data to be transferred. This is different from some clock-gated bus protocols.
Chip options:

Each slave has a dedicated SS/CS line.
When a particular slave is selected, it activates the MISO line, indicating that it is ready to send or receive data.

Regarding your question about full-duplex operation: in full-duplex SPI, both MOSI and MISO lines can be active simultaneously, but they are not always transferring data at the same time. The data on the MISO line might not be relevant during a write operation, but it becomes active during a read operation. The term “full-duplex” is used because the capability for simultaneous bidirectional communication exists, even if it’s not always utilized in every phase of the communication.

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