Spi clock assertion

SystemVerilog
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1

Hi ben,I want to write a assertion for the spi so when slave select signal(active low) is asserted then after the sclk starts, here i want to write assertion for sclk.
so i have tried it but i am getting of failure please help:


property sclk_freq;
  realtime current_time;
  @(posedge sclk)
     (1,current_time = $realtime) ##1 (time_period == ($realtime - current_time));
endproperty : sclk_freq
 
sclk_check:assert property(sclk_freq)
else
  `uvm_error("SPI_UVC_ASSRTIONS","CLOCK FAILED!!\n");

waveform:- Your text to link here…

Thank you

2

In reply to m_v:

I am not familiar with your system and your requirements for an assertion are incomplete.
The assertion that you wrote has nothing to do with whatever you are attempting to do.
Sorry!

3

In reply to ben@SystemVerilog.us:

Hi ben,
i have a main clock “bclk” and from that clock the a new clock is generated it is “sclk” and i wanted to write a assertion on the “sclk” and i am getting some unwanted error. can you help.

so when slave select(ss_n) is asserted(active low) as with respect to the “bclk” and the mosi and miso works on “sclk” , the “sclk” is generated in between of assertion of slave select(ss_n) and de-assertion of slave select(ss_n), also you can check from the waveform also.

link :- waveform…
Thank you.

4

Hi,ben one another question i want to write assertion on mosi line that mosi line must be stable between 2 posedges of the sclk how it can be done please check the Waveform….

Thank you.