Sparse Memory creation in systemverilog

SystemVerilog
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1

Hi,

I’m trying to create sparse memory for DDR3 simulation and depth could be vary from 128Mb to 64Gb.
In my simulation model Memory depth will vary as per MEM_SIZE = 128Mb to 64Gb, I want fill only some specific locations in memory like 2^10,2^17,2^4…etc.
But I’m not able to configure memory depth at simulation starting time,
Could anyone suggest me that how to create Sparse Memory.

I’m creating Sparse memory with associative array.

logic [`DATA_WIDTH-1:0] mem[*];

        if(we)
	begin
	 mem[addr] = data_in;
    	 $display("\tNumber of entries of Memory%0d",mem.num());
    	 $display("\tSize of Memory%0d",mem.size());

end
else   data_out  <= mem[addr];
2

In reply to balashyamu@gmail.com:

Never use the wildcard index type for an associative array.
Declare an address width and use that as the index type.

parameter MEM_SIZE = 2**27; // 128MB
parameter DATA_WIDTH = 64;
parameter ADDRESS_WIDTH = $clog2(MEM_SIZE*8) - DATA_WIDTH/8;

typedef logic [DATA_WIDTH-1:0] data_t;
typedef logic [ADDR_WIDTH-1:0] addr_t;

data_t mem[addr_t];
3

Hi Dave,

Isn’t the following incorrect?

parameter ADDRESS_WIDTH = $clog2(MEM_SIZE*8) - DATA_WIDTH/8;

It should be

parameter ADDRESS_WIDTH = $clog2(MEM_SIZE*8) - $clog2(DATA_WIDTH);