Solution for hierarchical reference in array instance

SystemVerilog
1

I have a piece of RTL code instantiates two memory models in array. I am looking for help how to access the variables in the memory model through hierarchical path. Here is the illustration


// This is the design RTL
module mem_model();
  int i_array[1024];
endmoudle

module cpu_ram
  mem_model my_ram_inst[2];
endmodule

I want to write a monitor that binds into mem_model that monitors/access i_array content. Question is how can I construct the hierarchical path to access the i_array?


bind mem_model mem_monitor my_monitor();
module mem_monitor
  <path_to_array>.i_array[0] = 1;     // how to construct <path_to_array>? 
endmodule

To my knowledge, <path_to_array> should be the instance name of mem_model, which is different on two instances. Is there any way to construct <path_to_array> by parameter?

2

In reply to Michaelotus:

You can use an upwards reference since this module is being bound into mem_model.

module mem_monitor
  mem_model.i_array[0] = 1;    
endmodule
3

In reply to dave_59:

Thanks Dave. By module name works. A good learn.