What is the difference between Zero-Delay Simulation, Delta-Delay Simulation and Unit-Delay Simulation in Gate Level Simulation.
In Verilog gate-level simulations, gate level cell models specify propagation delays in a number of different ways. The two most common are
- Path or pin-to-pin delays from an input pin to an output pin of a cell.
- Distributed delays across the individual gates that make up a cell.
Getting accurate gate-level timing costs some amount of simulation performance. To improve performance, simulation tools allow you to specify either
- Delay Mode Zero, which ignores all gate delays and sets them to 0, or
- Delay mode unit, which sets all gate delays to 1, one unit of the smallest time precision.
This prevents the gates from rippling events over a wide time period, but may cause race condition depending on how the cell library is modeled.
I have never heard the term Delta-Delay Simulation, used in the context of the other delay modes in a gate-level simulation.