Simulation time callback

SystemVerilog
1

I am using simulation time callback(cbAfterDelay) in my code. code snippet given below

s_vpi_time *time_p = malloc(sizeof(s_vpi_time)); 
time_p->real    = real_s_vpi_time;
time_p->type    = vpiSimTime;

s_cb_data *cb_data_p = malloc(sizeof(s_cb_data));
cb_data_p->obj          = signal_handle;
cb_data_p->user_data    = (void*)user_data;
cb_data_p->reason       = cbAfterDelay;
cb_data_p->cb_rtn       = cb_func;
cb_data_p->time         = time_p;
cb_data_p->value        = NULL;

return cb_data_p;

Here I am not getting multiple callbacks. But if “type = vpiScaledRealTime;” then multiple callbacks will happen.According to my design I am registering the callback multiple times and the requirement is getting the simulator internal(default) timescale.

2

In reply to Anjali_Ekkattiri:

I would have to see the actual delays you used and the timescales involved in your code. You might try set up a small self-contained testcase to make sure there are no other issues involved. VPI usage might need more help than can be provided on this forum; you might want to talk with your tool vendor directly for support.