Hi Team,
I am trying to simulate VHDL design file with UVM Verification components Environment in Questasim I created package file and included all the verification components. arinc_pkg.sv I am facing compilation error as shown below
** Error: (vlog-13069) ** while parsing file included at C:/Users/40034945/Downloads/UVM_files/arinc_pkg.sv(17)
** at Tb_advb_framer_top_uvm.sv(8): near “module”: syntax error, unexpected module, expecting class.
The error is showing in the Tb_advb_framer_top_uvm.sv (Tb_ top) file.
Design file requires unisim library I had compiled 3rd party simulators in Vivado 2023.1 version and I gave destination location in the Questasim installation path.
You have a syntax error and have not shown any code. Note that the error could be in the code that comes before the error.
Hi Dave,
Here I am attaching the package (arinc_pkg )and Tb_advb_framer_top_uvm.sv (tb_top) files.
package file:
package arinc_pkg;
// Imports
`include "uvm_macros.svh"
import uvm_pkg::*;
// UVC includes
//`include "advb_framer_top.vhd"
`include "advb_seq_item.sv"
`include "advb_seq.sv"
`include "advb_seqr.sv"
`include "advb_driver.sv"
`include "advb_monitor.sv"
`include "advb_agent.sv"
`include "advb_scoreboard.sv"
`include "advb_env.sv"
`include "advb_test.sv"
`include "Tb_advb_framer_top_uvm.sv"
endpackage
`include "advb_interface.sv"
Tb_advb_framer_top_uvm file:
// The top module that contains the DUT and interface.
// This module starts the test.
/*import my_testbench_pkg_uvm::*;
`include "uvm_macros.svh"
import uvm_pkg::*; */
module tb_advb_framer_top;
//signal delcarations
localparam PIXEL_CLK_T = 144;
localparam ADVB_CLK_T = 140;
logic pixel_clk,advb_clk;
// Instantiate the interface
advb_interface intf( .i_pixel_clk(pixel_clk),
.i_advb_clk(advb_clk));
advb_framer_top DUT(
.i_pixel_clk(intf.pixel_clk),
.i_advb_clk(intf.advb_clk),
.i_reset_n(intf.i_reset_n),
.i_write_en(intf.i_write_en),
.i_pixel_data(intf.i_pixel_data),
.o_data_valid(intf.o_data_valid),
.o_advb_frames(intf.o_advb_frames));
//--------------------------------------------------------
// pixel_clk Clock generator
//--------------------------------------------------------
initial begin
pixel_clk = 0;
forever #PIXEL_CLK_T pixel_clk = ~pixel_clk;
end
//--------------------------------------------------------
// advb_clk Clock generator
//--------------------------------------------------------
initial begin
advb_clk = 0;
forever #ADVB_CLK_T advb_clk = ~advb_clk;
end
//--------------------------------------------------------
//Interface Setting
//--------------------------------------------------------
initial begin
uvm_config_db #(virtual advb_framer_top) ::set(null, "*","vif", intf);
end
//--------------------------------------------------------
//Start test
//--------------------------------------------------------
initial begin
run_test("advb_test");
end
//-----------------------------------------------------------------------------------------------------------------------
//-------To run the simulation for a particular duration----------
//Here we are running the simulation only for 998 ms because one full video image --
//(i.e., 30 containers) will be completed by that time. --
//----------------------------------------------------------------------------------------------------------------------
initial begin
#998;
$display("End of simulation!");
$finish();
end
endmodule
A module cannot be defined inside a package; directly or `included.