Simple way to connect DUT with Interface

SystemVerilog
1

Is there an easy way to connect the DUT with interface?
for example, implicit connection like .*, but I don’t see how it works here.

module top;
my_ifc ifc;

//TO CONNECT IFC TO DUT
//usually we do this..
my_dut dut(.a(ifc.a),.b(ifc.b));

//is there a way to do something like this
my_dut dut(.*);

endmodule

interface my_ifc;
logic a;
logic b;
endinterface

module my_dut;
input a;
output b;
// codes
endmodule
2

In reply to pepes:

The wildcard named port connections (.*) requires that the port name and data types are equivalent, so you can’t use an interface in this manner.

However, you can use an interface as a module port.


interface simple_bus(input logic clk); // Define the interface
  logic req, gnt;
  logic [7:0] addr, data;
  logic [1:0] mode;
  logic start, rdy;
endinterface: simple_bus

module memMod(simple_bus a); // simple_bus interface port
  logic avail;
// When memMod is instantiated in module top, a.req is the req
// signal in the sb_intf instance of the 'simple_bus' interface
  always @(posedge a.clk) a.gnt <= a.req & avail;
endmodule

module cpuMod(simple_bus b); // simple_bus interface port
...
endmodule

module top;
  logic clk = 0;
  simple_bus sb_intf(.clk(clk)); // Instantiate the interface
  memMod mem(.a(sb_intf)); // Connect interface to module instance
  cpuMod cpu(.b(sb_intf)); // Connect interface to module instance
endmodule