In reply to Chandra Shekar N:
The braces {} represent the concatenation operator, which always returns an unsigned result. In this example, there is only one operand in the concatenation. So the only effect it has is casting the signed result of $random operand to unsigned. (btw, you have the example generated output swapped).
This is an obscure way of coding. It would be much more advisable to write
add = $unsigned($random) % 10;
In SystemVerilog, $urandom should always be used instead of $random. Besides returning a 32-bit unsigned value, it also has much better seeding and stability. See section 18.14 Random stability in the IEEE 1800-2017 SystemVerilog LRM.