Having recently referred Verilog Basics for SystemVerilog Constrained Random Verification , I have been tempted to try out signed Arithmetic in Constraints .
[I] CODE 1
rand bit [3:0] b[3]; // Unsigned by default !!
constraint NEG_ELEMENTS { foreach(b[i])
signed'(b[i]) == -1 ; // Sign Cast !!
}
Here are my thoughts on the working for the above code ( Feel free to correct me ) ::
(i) -1 is by default 32-bit signed , hence the expression is Evaluated as Signed.
Due to unequal size , b[i] would be extended to 32-bits . However due to signed'() Cast , we would perform Sign-Extension based on MSb !!
**[Q1] Shouldn't each element of Array b , be Constrained to be 4'b1111 ??**
[ I observe different Output on Licensed Simulators , hence the Confusion ]
[I] CODE 2
class SIGN_ADD ;
typedef bit signed [2:0] bitsign ;
rand bitsign a , b , c , d ;
rand bit signed [3:0] sum ;
constraint SIGN_ADDITION { sum == ( c < d ) + a + b ; } // c and d Unconstrained , right ??
endclass
SIGN_ADD obj ;
initial begin
obj = new() ;
if ( obj.randomize() )
$display("Success with %p",obj);
else
$display("Fails");
Each Operand would be made 4-bit due to Unequal Size of the Operands ( Table 11-21 LRM )
So Sign-Extension for a , b , c and d
The Output is Interesting
Success with '{a:7, b:6, c:2, d:5, sum:-2}
Success with '{a:3, b:6, c:6, d:0, sum:-7}
a , b , c and d are 3-bit Signed .
Hence the Max Negative Value for them would be -4 , Max Positive Value would be 3 ( But look at the Output !! )
LRM 11.8.1 ::
(1) Reduction Operator results are unsigned, regardless of the operands
So result of ( c < d ) is 1’b0 / 1’b1 making the entire expression Unsigned !! [ Verilog Basics !! ]
Which might be the reason I see values greater than 3 for a and b .
**Any additions to my understanding would be appreciated .**
[Q2] But shouldn’t a and b have values defined by Digital Basics ( b/w -4 and 3 ) ??
[Q3] An in-line constraint using ::
if ( obj.randomize() with { a < 0 ; b < 0 ; )
**Gives Constraint Failure !! , Not Sure why ??**
Thanks