Signal should not be stable for particular window

SystemVerilog
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1

Hi,

Lets say, I have two signals c_en and c_in,
Now I want to check that c_in (clk) should not be stable during the c_en is asserted,
Not necessary it should be continues toggling, but should not be stable throughout that window(that is c_en is asserted).

Please suggest some efficient assertion.

2

In reply to Shikhar Bhardwaj:

This might work
assert (c_en == 1) |-> !($stable(c_in))