In reply to dave_59:
Thanks, Dave. I must admit it was more or less a hypothetical “simulator-and-verilog” question. I agree, that there are numerous ways to avoid this behaviour, when it comes to the real issue (it was an easy fix, like you’ve said, with a delay), but I was more concerned about general idea: that standard verilog facilities do not provide a reliable way to sample signals for “reactive” (i.e. testbench) purposes and what to do about it.
In reply to Srini @ CVCblr.com:
I’ve taken a look at a program block and it seems to do what I was hoping to have. I’ll make some tests with delta glitches to see if it holds up. Thanks!
Could you please describe in a nutshell why there are opponents of this?
Best Regards,