In reply to artemonster:
Greetings all,
So, shall a delta-cycle signal change event really trigger suspended testbench blocks?
Are there any SystemVerilog constructs that would allow to safely wait for a signal (i.e. evaluate from Observed or Reactive region?)
Best Regards,
Since you asked and mentioned reactive region - in SV there is a construct called program block. Given this is MENT specific forum and there are some very strong opponents (valid reasons I must admit) of this construct in MENT, you may get different opinion.
Good Luck
Srini
www.verifworks.com