In reply to artemonster:
The simplest thing to do is put the signal through a continuous assignment with a delay larger than any glitch you want to filter. If it’s only 0-delay glitches you are concerned about then #1 will do. If you ever get into gate-level simulations, you may need a larger delay.
Another thing to consider is if a signal output from the DUT truly asynchronous coming from the perspective of an RTL simulation. Is there some clock you could use to sample it? Or is the some asynchronous event from the stimulus that you could use to sample the event?
There are probably a number of other solutions I could go into if this does not work for you.