Dear All,
I would like to perform shift register kind of operation in the systemverilog either in class or module using dynamic array. This is the scenario, where i get the data at 0th index of dynamic array at some periodic interval say 1.1 ns & below is my code snippet:
[code]
module m1;
bit[3:0] sv_i_da[];
bit [3:0] loop1, out1;
initial
begin
loop1=0;
sv_i_da = new[5];
while (loop1 < 5)
begin
sv_i_da[0]= $urandom;
for(int i = 0; i < loop1 ; i++)
sv_i_da[i+1] = sv_i_da[i];
#1.1;
out1 = sv_i_da[4];
$display("Time:%0t--sv_i_da[%0d]=%0d,sv_i_da =%0p,out1=%0d",$realtime,0,sv_i_da[0],sv_i_da,out1);
loop1 = loop1 + 1;
end
end
endmodule:m1
And The output is like as below:
Time:1100000–sv_i_da[0]=12,sv_i_da ='{'hc, 'h0, 'h0, 'h0, ‘h0} ,out1=0
Time:2200000–sv_i_da[0]=2,sv_i_da =’{'h2, 'h2, 'h0, 'h0, ‘h0} ,out1=0
Time:3300000–sv_i_da[0]=15,sv_i_da =’{'hf, 'hf, 'hf, 'h0, ‘h0} ,out1=0
Time:4400000–sv_i_da[0]=7,sv_i_da =’{'h7, 'h7, 'h7, 'h7, ‘h0} ,out1=0
Time:5500000–sv_i_da[0]=11,sv_i_da =’{'hb, 'hb, 'hb, 'hb, 'hb} ,out1=11
And my expectation for sv_i_da would be:
Time:1100000–sv_i_da[0]=12,sv_i_da ='{'hc, 'h0, 'h0, 'h0, ‘h0} ,out1=0
Time:2200000–sv_i_da[0]=2,sv_i_da =’{'h2, 'hc, 'h0, 'h0, ‘h0} ,out1=0
Time:3300000–sv_i_da[0]=15,sv_i_da =’{'hf, 'h2, 'hc, 'h0, ‘h0} ,out1=0
Time:4400000–sv_i_da[0]=7,sv_i_da =’{'h7, 'hf, 'h2, 'hc, ‘h0} ,out1=0
Time:5500000–sv_i_da[0]=11,sv_i_da =’{'hb, 'h7, 'hf, 'h2, 'hc} ,out1=11
Need your inputs in this code to achieve above result or is there any approach to achieve it using right shift operator in dynamic array (like sv_i_da >> 1) or any other SV data types.
Your immediate inputs are highly appreciated.
Thanks for your help.