Shift and concatinate operator causes a problem of truncating MSB

SystemVerilog
1

I am in trouble when adjusting vector width using concatination.

As shown below, I want to generate 32bit value of “result32” from
16bit value of “sq” with its lsb 8bit shift left to 1.

Below, “case1” works fine(value is 0x18C).
But “case2” is incorrect(0x08C).
In case 2, what I try to do is adjusting vector width of rihgt and left hand to diminish warning message from lint tool(Shift left of 8bit vector is 9bit, so pad MSB23bit with 0 explicitly).

It seems that when result from the opearator: "sq[7:0] << 1 " is used as a part of concatination, the result is limited to 8bit, while in case of the result used directly, vector width is enhanced to 9bit.
Is this specified in LRM? (Both VCS and IES geenrates the same results.)

logic [31:0] result32;
   logic [15:0] sq;

   initial begin
      result32 = 32'h00000000;
      sq  = 16'h00c6;

      // case 1 
      result32 = sq[7:0] << 1;
      $display(">> %x", result32); // 0000018c
      // case 2 
      result32 = {23'h0_0000, sq[7:0] << 1};
      $display(">> %x", result32); // 0000008c

Thnak you.

2

And Questa would also give the same result as well.

The issue is that each operand of a concatenation is self-determined.

This is explained in section 11.6.2 Example of expression bit-length problem of the 1800-2009 LRM. Or look in any old Verilog LRM explaining the rules for expression bit lengths and self-determinism - it has always been this way.