Sharing values between 2 sequences

UVM
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2

In reply to tex_mex:

I usually use uvm_event_pool to communicate between components or sequences. uvm_event_pool also let you pass a data value from a sequence to another. Simple idea:

  1. read_sequence waits for a event (uvm_event) to be triggered using wait_trigger_data(address) task before it issues a read to address which is received from wait_trigger_data task.

  2. write_sequence initializes a value to address, then trigger and send address value to read_sequence using trigger(address) function.

Code example: http://verificationsharing.blogspot.sg/2018/03/uvm-case-study-uvm-event.html