Setup and Hold time

SystemVerilog
1

If Set up and hold time fails then what happens?Please suggest me

2

In reply to truptipatro:

Then might not get desired behavior always. As FF is preparing output for you in setup-hold region, data should be stable in setup-hold window.

In theory FF should remain in meta-stable state indefinitely, but the way simulator behaves (practically) FF output will go to either ‘0’ or ‘1’ in the case.

3

In reply to MayurKubavat:
Digital simulators do not respect the setup and hold times, as they do do not model the metastability regions. Setup and hold times are typically checked by static timing analyzers.
In hardware, a setup or hold violation will cause a FF with inputs in the metastability region (as the signal changes from one level to the other) to flip to one level or another; there might be a toggle. This is because FF are designed with latchup (feedback). In fact, one way to make am oscillator is to take the output of an inverter and tie it back to its input.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

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4

In reply to MayurKubavat:

Thanks.