Setting the interface handle into config tb from top tb module

SystemVerilog
,
2

In reply to jaswanth_b:

You don’t mention what kind of error you are getting (compilation, run time, wrong value, etc), so these are some general recommendations:

  • Only target uvm_test_top with your interface handle
  • Use ‘null’ for context when at the top testbench level
  • Don’t use ‘*’ for a target as this can result in conflicts
  • Every string name used should be unique so that the test can assign the correct interface handle to the correct agent
  • In your test, get each handle and assign it to each agent’s (or environment) configuration object

module top_tb;
// ports

// i have a genvar for loop 
genvar i;
for (i=0; i<5; i++) begin : gen
  //interface instance
  xyz_if m_if;

  //module instance to which the interface is passed 
  module1 m1(m_if);
 
  // i am trying to set the same if into config db here 
  initial begin
    uvm_config_db#(virtual xyz_if)::set(null, "uvm_test_top", $sformatf("vif%0d",i), m_if);
  end
end //for loop
endmodule