interface dut_if#(parameter L_DSP = `define_l);
// signals
endinterface
module tb;
generate
for(genvar i =0; i < L_DSP; i++ ) begin
//dut_if#(L_DSP[i]) u_dut_if();
dut_if u_dut_if();
initial begin
uvm_config_db#(virtual dut_if#(L_DSP))::set(null,"*",$sformatf("u_dut_if_%0d", i),u_dut_if);
//uvm_config_db#(virtual dut_if#(L_DSP[i]))::set(null,"*",$sformatf("u_dut_if_%0d", i),u_dut_if[i]);
end
end
endgenerate
endmodule
class my_com extends uvm_component;
function void build_phase(uvm_phase phase);
super.build_phase(phase);
if (!uvm_config_db #(virtual dut_if )::get(null, "", "u_dut_if ", u_dut_if)) begin
`uvm_error("NOVIF", {"virtual interface not configured for ", get_full_name(), "u_dut_if "})
end
endfunction
endclass
for the commented:
//error: Bit-select or part-select dimensions do not match declaration****
for uncommented:
// error from class my_com : `uvm_error(“NOVIF”, {"virtual interface not configured for ", get_full_name(), "u_dut_if "})