Setting environment variables in SystemVerilog

SystemVerilog
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1

I am launching a simulation that is managed through a TCL script. The TCL script implements a while loop and in each loop a simulation is invoked.

TCL Script:


while {some_condition} {

    #some logic here
    run_simulation
    
    set env_var_a $::env(VAR_A)
    set env_var_b $::env(VAR_B)

    reset_simulation

    #rinse and repeat

Now in my SystemVerilog, right before the stop statement of the testbench I do the following


     setenv("VAR_A", $sformatf("%0f", result_a), 1);
     setenv("VAR_B", $sformatf("%0f", result_b), 1);

I have imported the DPI-C setenv function as


import "DPI-C" function int setenv(string name, string value, int override);

But the changes are not reflected back to the TCL script i.e., the VAR_A, and VAR_B variables are not modified.
What is the problem here?

Are the environment variables shallow-copies? In that case it makes sense that a parental process is not aware of any changes done by a child process.

Thank you in advance

2

In reply to Broxigar:

I think you answered your own question.