Sets of cover bins for mask bits

SystemVerilog
,
2

In reply to electron:

For your first question, you can put your bin values into an array, and use the array in the bin specification. See Verification Horizons - Siemens Software

For your second question, the coverpoint expression defines the value to be sampled. You could write

cp_masksLSB : coverpoint masks[15:0] {
    bins maskLSB = // Here I wanted to sample masks[15:0];
  }
 cp_masksMSB : coverpoint masks[31:16] {
    bins maskMSB = // Here                    masks[31:16];
  }

If that doesn’t work for you, take a look at the wildcard bin specification.