class A extends uvm_sequence_item;
`uvm_object_utils(A);
…
endclass
class B extends A;
// no uvm_object_utils(B)
add some new constraint …
endclass
I use: set_type_override_by_type(A::get_type(), B::get_type());
The compile log show: uvm_warning: original type and override type are identical.
Ques1: Is it because I have’t reigster B that results in set_type_overrid not take effect?
Ques2: If i did’t register B, why set_type_override has no compile error, while only a compile warning?
From the SystemVerilog perspective, the code is perfectly legal and would not generate a compiler error. One of the pitfalls of using macros is that you do not see the underlying code generated by the macro. I recommend learning the UVM without using any macros and introduce them later as you begin to understand what the macros are doing. See my blog post and this cookbook article to get a better understanding.
The reason B::get_type() does not generate a compiler error is because the `uvm_object_utils(A) macro declares A::get_Type for you, and since class B is an extension of class A, B inherits get_type() from A. So both of your arguments to set_type_override() call the same function. I’ts not until sumulation run time that the UVM checks that the two functions return a handle to the same wrapper object.
IMHO, it would be better to make these kinds of messages a UVM_ERROR by default. You can do that with the following statement:
uvm_top.set_report_severity_id_override(UVM_WARNING,"TYPDUP",UVM_ERROR);