Set constraint in uvm_seq_item

UVM
, ,
2

In reply to PIYUSH PANWAR:

You can certainly nest constraints in an implication or if-else constraint. There is an example of nesting in section 18.5.7.

But remember all constraint get assembled into a set of concurrent equations you can also write something like

constraint c_inst { inst==instr1 -> {opcode==8'h00; mode==2'b00; AddrCycle==0; DataCycle==0; Fflag==0;}
                    inst==instr2 -> {opcode==8'h00; mode inside {2'b01,2'10};  DataCycle=0; Fflag=0;}
                    mode==2'b01 -> AddrCycle=0;
                    mode==2'b10 -> AddrCycle=1;
  }