One very basic question related to uvm driver component
Generally we code as mentioned below
forever begin
seq_item_port.get_next_item(req);
vif.data <= req.addr;
....
....
seq_iem_done.item_done();
end
What will happen if we write like below. Will it wiggle to the DUT?
forever begin
seq_item_port.get_next_item(req);
seq_iem_done.item_done();
vif.data <= req.addr;
....
....
end
Please suggest me .
Yes, it will wiggle the DUT. However, you will need to be careful with respect to ‘req’.
When item_done() is called, the sequencer will re-arbitrate and have the selected sequence generate it’s next request. If your sequence re-uses ‘req’, then the new values will be used by the driver since they share the same ‘req’ handle.
It is recommended that you call item_done() when the transaction is completed on the bus. By doing this, you can also pass back data from the driver to the sequence by using data fields in ‘req’.
There are some interfaces where you will call item_done() before the transaction is complete (i.e. when you can have multiple transactions in process at the same time). In these cases, you will need to clone your ‘req’ and store them in the driver.