Sequence ##N ( No_match_sequence )

SystemVerilog
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4

In reply to ben@SystemVerilog.us:

Thank your Sir for your response.

Would like to hear your comments on the following

  1. Although ‘req’ is a non-degenerate (admits either a match/not match) one clock later we have a sequence that admits no match.
    Essentially the entire expression is equivalent to
non_degenerate_sequence_exp ##1 no_match_sequence_exp

Now this entire expression itself is a degenerate as it can never match. Hence it’s illegal
Is my understanding correct ?
2. Are the following two SVAs equivalent ?


sva_1:assert property( @(posedge clk) req ##1 (rdy[*0] ##0 ack) ); // (rdy[*0] ##0 ack) is no match i.e hard 0
sva_2:assert property( @(posedge clk) req ##1 (0) );
  1. How is that following concurrent assertions are considered legal ?

sva1:assert property( @(posedge clk) req ##1 (0) );
sva2:assert property( @(posedge clk) req ##1 0 );
sva3:assert property( @(posedge clk) 0 );

As these sequences can never match, shouldn’t these be considered degenerate sequences as well ? ( thereby making them illegal )