Sequence ##N ( No_match_sequence )

SystemVerilog
,
3

In reply to ben@SystemVerilog.us:

Note:


assert property( @(posedge ip_clk) req ##1 rdy[*0] ##0 ack); // Is legal because
req ##1 rdy[*0] ##0 ack // is reduced to 
req ##0 1 ##0 ack // using left associativity 
    
assert property( @(posedge ip_clk) req ##1( rdy[*0] ##0 ack ) ); // Is  illegal because 
( rdy[*0] ##0 ack ) is bracketed, thus, 
( rdy[*0] ##0 ack ) is degenerate.

Ben Cohen
Ben@systemverilog.us
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