In reply to nocsmsourabh:
In reply to nocsmsourabh:
Hi ,
you need to register the sequence_item with factory in order to use create method, try after including `uvm_object_utils lines in both the trans1 & trans2
class trans1 extends uvm_sequence_item;
`uvm_object_utils(trans1)
rand bit [7:0] data1;
rand bit [7:0] data2;
----
----
endclass
class trans2 extends uvm_sequence_item;
`uvm_object_utils(trans2)
rand trans1 t;
rand bit [15:0] data;
constraint D1
{
data == {t.data1, t.data2};
}
----
----
endclass