"Sequence is instantiated in a non-temporal context" error when reusing sequence inside property

[mzamek2]

My intent is to create several testpoints for crossing scenarios when events A, B, C… happen simultaneously.

My code:

    sequence A(signal, event);
        @(posedge event)
            (signal == 1'b1);
    endsequence

    sequence B(fmt,event);
        @(posedge event)
            (fmt==4'd5);
    endsequence

    property is_A_and_B(integer win);
        @(posedge clk)
        (A(bus1[win], bus2[win]) && B(bus3[win], bus2[win]));
    endproperty

    everything: cover property(is_A_and_B(3)); 

I’m getting this error in VCS:
Error-[SPIUNTC] Instance used in non-temporal context

can someone please explain what the issue is and what is a good way to achieve the intent?

[user49]

In reply to mzamek2:

• Your requirements are not clear.
• The error message is because you are using the wrong sequence ANDing operator.

• - && is a logical AND.
  - and is a sequence AND
  thus (a ##1 b) and (c ##[1:3] d)
  
  
• In “sequence A(signal, event);”, event is a type and not an argument.
  You can do sequence A(signal, event e);
• Your property definition is very unusual as you are using the clocking event as the leading clocking event (OK, should be like this), BUT then in “B(bus3[win], bus2[win])” you use a sequence as a clocking event. This is not how things are done typically.

Sequences can be used as clocking event, but they are rarely used as such. Below is code that simulates, though i am not much of a proponent of using sequences as clocking events; I never do that, but I address it in my SVA book.

import uvm_pkg::*; `include "uvm_macros.svh" 
module top; 
    timeunit 1ns;     timeprecision 100ps;    
	bit clk, a, b, c;  
    default clocking @(posedge clk); 
    endclocking
    initial forever #10 clk=!clk;  
    
    sequence q1; 
        @(posedge clk) a ##1 b; 
    endsequence 
    
    
    always  begin 
        @(q1) if(c!=1'b1) $display("%t error, c!=1", $realtime); 
    end 
    ap_q1c: assert property(@(q1) c);  // Unusal usage of sequence as clocking event  
    // typical usage:  @(posedge clk) q1 ##0 c; // 
    // Better usage:  @(posedge clk) q1 |-> c; // 
    
    initial begin   
        repeat(200) begin 
            @(posedge clk);  #2; 
            if (!randomize(a, b, c)  with 
            { a dist {1'b1:=1, 1'b0:=3};
            b dist {1'b1:=1, 1'b0:=2};
            c dist {1'b1:=1, 1'b0:=1};
        }) `uvm_error("MYERR", "This is a randomize error")
    end 
    $stop; 
end 
endmodule    

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

• SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
• Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
• A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
• Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
• Component Design by Example ", 2001 ISBN 0-9705394-0-1
• VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
• VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115

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