Sequence coverage in Interface clocking block

Coverage
, ,
1

Hi,
I need to ensure that 3 signals occur in all possible orders that they can (6 ways). For this, I am trying to write a sequence and then instantiate it in my interface class :

interface vpp_sse_perf_cov_if (input clock, input reset);
  logic data;
  logic valid;
  logic stall;
  logic end_of_seq;
  logic another;

 sequence rel_position(logic a, logic b, logic c, logic d);
       a[=1] ##1 b[=1] ##1 c[=1] ##1 d;//a should be true(its last occurence is) followed (at some point)by b, followed by c, followed by d.  
 endsequence

 logic sig1 = stall & another;  
 clocking mon_cb @(negedge clock);
  input stall;
  input valid;
  input data;
  input end_of_seq;
  input another;
  input sig1;
 
 case7_1_2_3 : cover property (rel_position(sig1,stall,valid,end_of_seq)) ;
 case7_1_3_2 : cover property (rel_position(sig1,valid,stall,end_of_seq)) ;
 case7_2_1_3 : cover property (rel_position(stall,sig1,valid,end_of_seq)) ;
 case7_2_3_1 : cover property (rel_position(stall,valid,sig1,end_of_seq)) ;
 case7_3_1_2 : cover property (rel_position(valid,sig1,stall,end_of_seq)) ;
 case7_3_2_1 : cover property (rel_position(valid,stall,sig1,end_of_seq)) ;

 endclocking : mon_cb

 modport mon_mp (clocking mon_cb, input clock, reset);
endinterface

The above code is giving me compile errors : “Expecting the keyword ‘endclocking’”
The error appears on the 1st cover statement for the sequence.

Any ideas what I am doing wrong and how it could be changed?

Thanks,
Romi

2

You do not put assertion/cover directives inside a clocking block, only sequence and property declarations. Put the cover directives outside the clocking block. In your case, as in most cases, there is no benefit in putting the sequence declaration inside the clocking block. Just put @(negedge clock) in the sequence.