In reply to amitr5:
I would use as the clocking event for the assertion the source clock (src_clock), and then for the wait number of ccles the dest clok. Thus
// More comments below, as this may not be what you want.
ap_src2dest: assert property (@(posedge src_clock) source_data |->
@(dest_clock) ##[3:5] dest_data );
A few comments:
- Am puzzled by the name of the signals “source_data” “dest_data”. Is this an integer? or is it a sync single bit signal. For the above to work, it has to be an expression the way the assertion is written If it’s a data bit, you want to check that the signal crosses the clock boundary, regardless of the value of what you call “data”. In theat case, I would prefer:
ap_src2dest_to1: assert property ( @(posedge src_clock) $rose(src_data_bit)|->
@(dest_clock) ##[3:5] $rose(dest_data_bit));
ap_src2dest_to0: assert property (@(posedge src_clock) $fell(src_data_bit)|->
@(dest_clock) ##[3:5] $fell(dest_data_bit));
I
2. The folloing is illegal as a leading clocking event:
(@(posedge dst_clock) || @(source_data)) , (@(posedge dst_clock) or @(source_data))
Ben Cohen
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