In reply to pawan:
The reason the sampling is in the Prepone region is because this is when all the signals are steady, just before being clocked.
Consider a posedge of clk at time t, and a 10ns clock.
- RegA changes value at time t+1ns
- Logic following RegA takes anywhere between 1 to 6 ns, thus the “D” input to the next stage changes at time t+2ns up to t+7ns
- The next stage reg requires a 1ns setup time.
Question: When do you want to do you verification? at time t+delta time, or t+1ns? or t+ 6ns?
The answer is NO, you want to do your tests JUST BEFORE the clocking event , in the Prepone region.
Another example: You go to a restaurant. You want a steak (the Prepone region).
- Waiter comes in (the posedge of clk)
- You (the Reg)say “I already decided just before I came in on the steak”
- Your friend (gating logic) says “No, steak is unhealthy, he’ll take the fish”
What do you want to test as to what gets selected for the next transaction? The steak or the fish? It’s the steak, of course, because that decision gets modified in the next time frame. The assertion for this would be
ap: assert property(@(posedge clk) steak |=> fish);
It’s the decision of the “steak” that causes the logic for the next stage (what gets cooked) to be the fish.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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