Sampling logic in UVM monitor : on all the clocks

In reply to chr_sue:

Its a simple Block ram with write_en control. wr_data is written in the mem at addr wr_addr when wr_en is high.
There is no rd_en control. rd_data comes out for rd_addr in next clock cycle.
I could take care of it now. But default value setting drive task of driver is creating some issue. will get back, if i dont get it.
thank you!